--------------------------------------------------------------------------------
-- Copyright (c) 1995-2007 Xilinx, Inc.  All rights reserved.
--------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor: Xilinx
-- \   \   \/     Version: J.36
--  \   \         Application: netgen
--  /   /         Filename: datapath_synthesis.vhd
-- /___/   /\     Timestamp: Fri Apr 15 15:40:13 2011
-- \   \  /  \ 
--  \___\/\___\
--             
-- Command	: -intstyle ise -ar Structure -tm datapath -w -dir netgen/synthesis -ofmt vhdl -sim datapath.ngc datapath_synthesis.vhd 
-- Device	: xc4vlx15-12-sf363
-- Input file	: datapath.ngc
-- Output file	: C:\Xilinx92i\Practicas\Datapath\netgen\synthesis\datapath_synthesis.vhd
-- # of Entities	: 1
-- Design Name	: datapath
-- Xilinx	: C:\Xilinx92i
--             
-- Purpose:    
--     This VHDL netlist is a verification model and uses simulation 
--     primitives which may not represent the true implementation of the 
--     device, however the netlist is functionally correct and should not 
--     be modified. This file cannot be synthesized and should only be used 
--     with supported simulation tools.
--             
-- Reference:  
--     Development System Reference Guide, Chapter 23
--     Synthesis and Simulation Design Guide, Chapter 6
--             
--------------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity datapath is
  port (
    is_interrupt : in STD_LOGIC := 'X'; 
    is_reti : in STD_LOGIC := 'X'; 
    is_ret : in STD_LOGIC := 'X'; 
    int_req : in STD_LOGIC := 'X'; 
    is_misc : in STD_LOGIC := 'X'; 
    we : in STD_LOGIC := 'X'; 
    is_branch : in STD_LOGIC := 'X'; 
    d_enable : in STD_LOGIC := 'X'; 
    d_clk : in STD_LOGIC := 'X'; 
    d_clr : in STD_LOGIC := 'X'; 
    is_jump : in STD_LOGIC := 'X'; 
    pc_in : in STD_LOGIC_VECTOR ( 9 downto 0 ); 
    instr_op_code : in STD_LOGIC_VECTOR ( 3 downto 0 ); 
    flags_in : in STD_LOGIC_VECTOR ( 1 downto 0 ); 
    op_code : in STD_LOGIC_VECTOR ( 2 downto 0 ); 
    instr_reg_in : in STD_LOGIC_VECTOR ( 17 downto 0 ); 
    d_in : in STD_LOGIC_VECTOR ( 9 downto 0 ); 
    a_in : in STD_LOGIC_VECTOR ( 2 downto 0 ); 
    proc_state : in STD_LOGIC_VECTOR ( 2 downto 0 ) 
  );
end datapath;

architecture Structure of datapath is
  signal N4 : STD_LOGIC; 
  signal N5 : STD_LOGIC; 
begin
  XST_GND : GND
    port map (
      G => N4
    );
  XST_VCC : VCC
    port map (
      P => N5
    );

end Structure;

